Signal transmitting device suited to fast signal transmission

ABSTRACT

A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

BACKGROUND OF THE INVENTION

The present invention relates to technique of transmitting a signalbetween elements such as a CPU and a memory device or memory IC (forexample, between digital circuits each composed of CMOS elements orfunctional blocks of CMOS elements), and, more particularly totechniques of quickly transmitting a signal through one bus in which onemain transmission line has plural elements connected thereto.

As a technique of quickly transmitting a signal between digital circuitseach composed of a semiconductor integrated circuit, there has beenproposed a technique of a low-amplitude interface for propagating asignal having a signal amplitude as low as about 1 volt.

As a representative example of such a low-amplitude interface, a GTL(Gunning Transceiver Logic) interface or a CTT (Center TappedTermination) interface has been heretofore proposed. These low-amplitudeinterfaces are discussed in detail in pp 269 to 290 of NikkeiElectronics, Nov. 27, 1993.

FIG. 1 shows a prior art arrangement of such a low-amplitude interfacein which one main transmission line has plural branched lines.

A numeral 100 denotes a transmission line terminated by terminationpower supplies 60 and 61 and termination resistors 50 and 51. Thetransmission line 100 is connected to a driving circuit block 1 andreceiving circuit blocks 2, 3 and 4.

The transmission line 100 has an impedance of 50Ω. Each of branchedlines 11 to 14 has an impedance of 50Ω. Each of the terminatingresistors 50 and 51 has an impedance of 50Ω. Each voltage of theterminating power supplies 60 and 61 is 0.5 volt. The sending or drivingcircuit 21 has an on resistance of 10Ω.

When the driving circuit 21 is at a logical “High” output, the circuit21 operates to connect the transmission line 11 to a 1-volt power supply(not shown). When the driving circuit 21 is at a logical “Low” output,the circuit 21 operates to connect the transmission line 11 to theground, that is, a 0-volt power supply (not shown). Numerals 32 to 34denote receiving circuits included in a receiving circuit block,respectively. These receiving circuits compare received signals with thereference voltage V_(ref) to determine if the received signal is a Lowor High level. In this arrangement, V_(ref) is set at 0.5V.

Next, a description will be given as to how a signal is transmitted toeach point in FIG. 1 on this bus when the driving circuit 21 is switchedfrom the Low output to the High output. At first, a potential of thetransmission bus 100 is derived when the driving circuit 21 is at theLow output. The voltage at the point A on the transmission line at thistime corresponds to a voltage given by dividing the terminating powersource of 0.5 volt by the terminating resistances 50 and 51 and the onresistance of the sending circuit 21. That is, the voltage is derivedby:0.5V×10Ω/(10Ω+50Ω/2)=0.14(V)

Next, the potential will be derived of the transmission line whichoccurs when the output of the sending circuit 21 is switched from theLow output to the High output so that a signal is transmitted to a pointA of FIG. 1 as follows. Immediately after the output of the sendingcircuit 21 is switched, the power supply voltage is divided by theon-resistance of the sending circuit and the impedance 50Ω of thetransmission line 11. Hence, the potential boost at the point A isderived by:1V×50Ω/(50Ω+10Ω)=0.83 (V)The addition of the initial voltage 0.14 V and the voltage boost, thatis, 0.97 V corresponds to the potential at the point A.

The potential occurring when the waveform of the amplitude of 0.83 Vreaches the branch point B is derived as follows. If the transmissionline 100 is viewed from the transmission line 11, since the transmissionline 100 is divided into two, left and right parts, the virtualimpedance of the transmission line 100 if viewed from the transmissionline 11 becomes a half of an impedance 50Ω of the transmission line 100,that is, 25Ω. On the other hand, since the impedance of the transmissionline 11 is 50Ω, the mismatch of the impedance results in bringing aboutthe reflection of a signal at the point B.

The reflective coefficient is derived as follows.(50Ω−25Ω)/(50Ω+25Ω)=0.33This means that a one-third part of the signal amplitude of 0.83 Vtransmitted to the point A, that is, a signal of the amplitude 0.28 V isreflected and returned to the sending circuit side. The signal of theleft amplitude 0.55 V is transmitted to the transmission line 100 as afirst transmitted wave. Hence, the potential of the transmitted signalcorresponds to an addition of 0.55 V and the initial potential, that is,0.69 V.

When the signal having the amplitude of 0.28 V returned to the sendingcircuit reaches the sending circuit, the signal is mirror-reflected andreaches the point B again. A two-third part of the signal passes throughthe transmission line 100, while the remaining one-third part of thesignal is returned to the transmission line 11. According to such anaction, the signal travels to and fro on the transmission line 11 againand again. Each time the signal waveform reaches the point B, thetwo-third part of each waveform is output to the transmission line 100.By this operation, the amplitude of 0.83 V originally at the point A isdividedly transmitted to the transmission line 100 bit by bit.

The signal of 0.69 V which passed through the point B and transmitted tothe transmission line 100 reaches the point C. At this point, twotransmission lines are each made to have an impedance of 50Ω before thepassage of the signal. Hence, the mismatch of the forward synthesizedimpedance 25Ω to the impedance of 50Ω of the transmission line on whichthe signal has passed results in bringing about the reflection of thesignal.

The reflective coefficient is as follows:(50Ω−25Ω)/(50Ω+25Ω)=0.33

The potential of the waveform passed through the point C corresponds toa potential derived by multiplying the signal amplitude of 0.55 V at thepoint B by a transmittance ⅔ (=1−⅓) and adding the initial potential tothe multiplied value. That is,0.55V×⅔+0.14V=0.50 (V)

A similar reflection takes place at the point E or the point G. Thepotential at the point E is 0.38 V and the potential at the point G is0.30 V.

These results are shown in FIGS. 2A to 2C. FIG. 2A shows signals whichcome to and go out of the point C, that is, a signal of the point Bcoming to the point C and signals of the point D and the point E goingout of the point C. For explaining them clearly, the signal at the pointA is shown as well. Likewise, FIG. 2B shows signals which come to and goout of the point E. FIG. 2C shows signals which come to and go out ofthe point G. In FIGS. 2A to 2C, a numeral 201 denotes a signal waveformat the point A in FIG. 1. A numeral 202 denotes a waveform at the pointB. A numeral 203 denotes a waveform at the point C. A numeral 204denotes a waveform at the point D. A numeral 205 denotes a waveform atthe point E. A numeral 206 denotes a waveform at the point F. A numeral207 denotes a waveform at the point G. A numeral 208 denotes a waveformat the point H. When the signal drops, the same thing takes place. Thesignal waveforms at the drop of the signal are as shown in FIGS. 3A to3C. In FIG. 3, numerals 201 to 208 denote signal waveforms at the pointA to the point H shown in FIG. 1, respectively.

From the situation described above, it is understood that the use of theconventional signal transmitting circuit makes it impossible to allowthe first signal at the point A indicating a High level from the drivingcircuit 21 to exceed the reference voltage Vref (0.5 V in the abovecondition) at all of the receiving circuit blocks for establishing thatthe signal is at the High level. In other words, due to the large degreeof reflection at the various points B, C, E and G, the original Highlevel voltage at the point A for the first signal is attenuated to verylow levels of voltage that will not exceed the reference voltage V_(ref)at the receivers. Therefore, even though the sending circuit 21 isindicating a High level, the receivers 32, 33 and 34 will not be able torecognize this for the first signal. Eventually, after repeated signals,the level of voltage at points B, C and D will increase to levels muchcloser to the level at point A, but, until this occurs, the receiverswill not be able to recognize the High level.

The signal entering each branched line at the branch point C, E or G,like the transmission line 11, is reflected over and over inside of thebranched line. When the reflected waveform returns to the branch point,the two-third part of the signal goes to the transmission line 100. Thisbrings about a waveform distortion on the transmission line 100.

As mentioned above, in the foregoing prior art, the reflections takeplace at each branch point. The potential drops resulting from thereflections are overlapped with each other. Hence, the rise of thesignal potential is delayed in a remote place of the driving circuit.This results in disadvantageously increasing the delay time, and therebyprevents quickly transmitting the signal.

Further, the signal entered into the receiving circuit block isreflected in the receiving circuit part and then goes into thetransmission line 100. This also results in disadvantageously distortingthe signal waveform, thereby lowering the reliability of the signaltransmission.

To speed up the signal transmission and make the signal amplitude on theline 100 smaller, the above prior art is arranged so that the supplyvoltage is 1 V. In the circuit discussed in the aforementioned paper, toachieve an amplitude of 1 V at the normally used power supply of 3.3 V,the driving circuit is arranged to give a special value of 100Ω to itson-resistance for realizing a small amplitude.

The special value given to the on resistance as mentioned in the paper,however, makes the widely available transistors having an on resistanceof about 10 W useless. In other words, specially designed transistorsare required.

Further, such a higher on resistance given to the sending circuit 21leads to increasing the power consumption of the driving circuit,thereby disadvantageously increasing the overall power consumption.

As another known prior art arrangement relevant to the presentinvention, U.S. Pat. No. 4,922,449 to Donaldson et al may be referredto. This U.S. Patent discloses a technique of providing a resistorbetween a circuit block and an inter-block signal transmission line in acircuit line structure having plural circuit blocks containing a drivingcircuit and a receiving circuit and the inter-block signal transmissionline for propagating a signal between the circuit blocks. The object ofproviding the resistor therebetween is for reducing passage currentappearing at the time of signal collision by the source switchingoperation, that is, reducing the amplitude of the signal on theinter-block signal transmission bus. The resistance is set as 20 W to 40W. This resistance may bring about a signal reflection at a branch pointbetween the transmission line inside of the circuit block and theinter-block transmission line. The signal reflection maydisadvantageously inhibit the realization of fast signal transmission.That is, this technique does not define any resistance based on arelation of an impedance between the inter-block signal transmissionline and the signal transmission line inside of the block.

Moreover, another prior art arrangement which provides a resistorbetween an inter-block signal transmission line and a signaltransmission line inside of the circuit block is disclosed inJP-B-54-5929. In this prior art arrangement, a resistor is provided onlybetween the circuit block on the side of the receiving circuit and theinter-block signal transmission line, but no resistor is providedbetween the circuit block provided with a sending circuit and theinter-block signal transmission bus. Like U.S. Pat. No. 4,922,449, asignal reflection takes place when the signal outputted from the sendingcircuit is transmitted onto the inter-block signal transmission bus. Asin the previously described arrangement, this signal reflection maydisadvantageously inhibit realization of fast signal transmission.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a signaltransmitting device, a circuit block, and an integrated circuit whichare arranged to overcome the foregoing disadvantages, suppress the dropof a signal potential on a transmission line having branched lines,prevent repetitive reflections in each branched line, and keep anamplitude of a signal small on the line, for quickly transmitting asignal.

To achieve the object in a preferred mode, a signal transmitting devicecomprises a first circuit block including a driving circuit for drivinga signal and an intra-block transmission line for transmitting a signalfrom the driving circuit to the outside of the circuit block, a secondcircuit block including a receiving circuit for receiving a signal andan intra-block transmission line for transmitting a signal to beinputted to the receiving circuit, and an inter-block transmission linefor transmitting the signal between the circuit blocks, wherein theinter-block transmission line is terminated by one or two elements eachhaving a resistance equal to or close to a characteristic impedancevalue of the inter-block transmission line. In addition, the resistanceof each of resistors 80 to 83 is provided with a resistance equal to orclose to a value obtained by subtracting a half of the impedance of theinter-block transmission line from the impedance of the intra-blocktransmission line.

In a circuit device having plural blocks each having both of a drivingcircuit and a receiving circuit, likewise, the inter-block transmissionline is terminated by one or two elements each having a resistance equalto or close to a characteristic impedance of the inter-blocktransmission line. Each intra-block transmission line is provided tohave a resistance equal to or close to a value obtained by subtracting ahalf of the characteristic impedance of the inter-block transmissionline from the impedance of the intra-block transmission line.

In the case where a package with a long lead frame such as quad flatpackage (QFP) or a pin grid array (PGA) is used in an integrated circuithaving a driving or a receiving circuit integrated thereon terminationis made to the inter-block transmission line, a resistor is provided forimpedance matching between the inter-block transmission line and theintra-block transmission line, and the impedance of the lead frame andthe impedance of the intra-block transmission line are matched.

In accordance with the present invention, by inserting a resistor havinga resistance close to a value derived by reducing a half of an impedanceof the line from the impedance of the branched line, it is possible toprevent repetition of reflections inside of the branched line andattenuate the amplitude of the transmission line by dividing theinserted resistance and the terminating resistance, thereby enabling toquickly transmit the signal.

In the case where a large number of branch points exist on theinter-block transfer line, the capacitance because of the existence ofthe resistors, the inter-block transmission line is not able to see thebranched line directly (i.e., the total of the transmission line loadcapacitance and the capacitance of the driving and receiving circuits).This is effective in suppressing the line impedance from being lowered.Further, the waveform distortion due to live-insertion can besuppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a conventional unidirectional transmissionline;

FIGS. 2A to 2C are charts showing signal waveforms (leading waveforms)appearing in the case of using the conventional transmission line;

FIGS. 3A to 3C are charts showing signal waveforms (tailing waveforms)appearing in the case of using the conventional transmission line;

FIG. 4 is a block diagram showing an embodiment 1 of the presentinvention;

FIG. 5 is a circuit diagram showing an example of a driving circuit;

FIG. 6 is a circuit diagram showing an example of a differentialreceiving circuit;

FIGS. 7A to 7C are graphs showing signal waveforms (leading waveforms)in the embodiment 1 of the present invention;

FIGS. 8A to 8C are graphs showing signal waveforms (tailing waveforms)in the embodiment 1 of the present invention;

FIG. 9 is a graph showing a waveform distortion occurring whenlive-insertion is executed in the case of using the conventionaltransmission line;

FIG. 10 is a graph showing a waveform distortion due to live-insertionin the case of using the circuit according to the embodiment 1 of thepresent invention;

FIG. 11 is a block diagram showing an embodiment 2 of the presentinvention;

FIGS. 12A to 12B are graphs showing waveforms occurring when the sendingcircuit is switched by using the conventional transmission line;

FIGS. 13A to 13B are diagrams showing waveforms of switching operationby driving circuit of the embodiment 2;

FIG. 14 is a block diagram showing an embodiment 3 of the invention;

FIG. 15 is a diagram showing a modification of the embodiment 3;

FIGS. 16A to 16C are graphs showing signal waveforms (leading waveforms)occurring in the case of the circuit according to the embodiment 3 ofthe present invention;

FIGS. 17A to 17C are graphs showing signal waveforms (tailing waveforms)occurring in the case of the circuit according to the embodiment 3 ofthe present invention;

FIGS. 18A to 18C are graphs showing signal waveforms (leading waveforms)occurring in the case of changing an impedance on a transmission line inthe circuit according to the embodiment 1 of the present invention;

FIGS. 19A to 19C are graphs showing signal waveforms (tailing waveforms)occurring in the case of changing an impedance on a transmission line inthe circuit according to the embodiment 1 of the present invention;

FIG. 20 is a circuit diagram showing an arrangement of the embodiment 3of the present invention in which a capacitor is used in place of theresistor;

FIG. 21 is a circuit showing another arrangement of the embodiment 3 ofthe present invention in which a capacitor is used in place of theresistor;

FIGS. 22A to 22C are graphs showing signal waveforms (leading waveforms)occurring in the case of using the arrangement shown in FIG. 20;

FIGS. 23A to 23C are graphs showing signal waveforms (tailing waveforms)occurring in the case of using the arrangement shown in FIG. 20;

FIG. 24 is a graph showing a signal waveform occurring in a circuitarrangement shown in FIG. 4;

FIG. 25 is a graph showing a signal waveform occurring in a case thatresistors 80 to 83 have smaller values in the circuit arrangement shownin FIG. 4;

FIG. 26 is a graph showing a signal waveform occurring in a case thatthe resistors 80 to 83 have larger values in the circuit arrangementshown in FIG. 4;

FIG. 27 is a block diagram showing an embodiment 4 of the presentinvention;

FIG. 28 is a sectional view showing a QFP package;

FIG. 29 is a sectional view showing a PGA package; and

FIG. 30 is a diagram showing an example of a device on which the QFPpackage is mounted.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment of the present invention will be described in detail withreference to the accompanying drawings.

FIG. 4 shows in fundamental block diagram, a first embodiment of aunidirectional transmission line to which the present invention isapplied.

In FIG. 4, a numeral 1 denotes a driving circuit block (unit) having adriving circuit 21. Numerals 2 to 4 denote receiving circuit blocksprovided with receiving circuits 32 to 34, respectively. The circuitblocks include resistors 80 to 83 and transmission lines 11 to 14,respectively. A transmission line 100 is connected to the circuit blocks1 to 4, and both ends of the transmission bus 100 are terminated by theresistors 50 and 51, each having a resistance equal to or close to acharacteristic impedance value of the transmission line 100.

In FIG. 4, the transmission line 100 has an impedance of 50Ω. Thebranched lines 11 to 14 each have an impedance of 100Ω. Each of thetermination resistors 50 and 51 has a resistance of 50Ω. Terminatingpower supplies 60 and 61 operate to supply a voltage of 1.5 V. Thedriving circuit 21 has an on resistance of 10Ω.

The driving circuit 21 operates to connect a transmission line to a3V-power supply (such as 62 in FIG. 5) when the driving circuit 21 holdsthe output high or connect the transmission line to a ground potential(such as 63, in FIG. 5) when the driving circuit 21 holds the outputlow. In FIG. 4, numerals 32 to 34 denote receiving circuits.

The resistors 80 to 83 are each defined to have a resistance of 75Ω. Themethod of defining the resistance will be described later.

It is noted that in this embodiment, the transmission line 100 isterminated at both of the ends. However, it may be terminated at one endby just one resistor, if preferred. Further, this embodiment providesthree receiving circuit blocks each having a receiving circuit. However,the present invention is applicable to a signal transmission deviceincluding at least one block having the receiving circuit.

FIG. 5 shows an example of the sending or driving circuit 21 used in thearrangement of FIG. 4. This driving circuit 21 is a push-pull drivingcircuit composed of a pull-up transistor 70 and a pull-down transistor71.

The pull-up transistor 70 shown in FIG. 5 is made of an N-channel MOSfield-effect transistor (NMOS). The material of the transistor 70 is notlimited to NMOS. For example, a P-channel MOS field-effect transistor(PMOS) may be used for making the transistor 70.

A low-amplitude driving circuit provided with the push-pull drivingcircuit is discussed in detail in the Nikkei Electronics paper referredto previously as a prior art arrangement. In this paper, however, thedriving circuit uses a transistor with as high an on-resistor as about100Ω. On the contrary, the present invention uses a transistor with anon resistance of about 10Ω which is now widely available. The presentinvention may use the conventional driving circuit, because the sum ofon-resistance of the resistors 80 to 83 added in this embodiment and thetransistor on resistance of about 10Ω is close to the on resistance of100Ω of the prior art device so that the amplitude on the transmissionbus 100 is approximately the same magnitude as that of the prior art.

For example, assume that the impedance and the termination resistor ofthe transmission line 100 is 50Ω, the impedance of the branched line is100Ω, the terminating power supply feeds a voltage of 1.5 V, and thepower supply for the driving circuit feeds a voltage of 3 V. With theseassumptions, the signal amplitude becomes 0.6 V on the transmission lineused in the foregoing paper indicating the use of the transistor withthe on resistance of 100Ω, and the amplitude is substantially equal tothe amplitude of 0.68 V of the transmission line 100 shown in FIG. 4.

By lowering the on-resistance of the driving circuit 21 from 100Ω to10Ω, it is possible to reduce the power consumed in the driving circuit.For example, in the above condition, the prior art device arranged touse an on resistance of 100Ω consumes a power of 14.4 mW, while thepresent invention may greatly reduce the power consumption down to 1.9mW. Moreover, the present embodiment may use a driving circuit having anon-resistance of 10Ω or more, concretely, about 50Ω. Such a drivingcircuit may offer the same effect as above.

Next, an example of the receiving circuits of FIG. 4 is shown in FIG. 6.This receiving circuit is a differential receiving circuit fordetermining if an input signal is logically High or Low based on whetheror not an input voltage is higher or lower than the reference voltageV_(ref). The reference voltage used herein may be produced inside of anintegrated circuit. However, if noises appearing inside of theintegrated circuit or noises which have entered from the outside causethe power supply to fluctuate, the reference voltage may fluctuateaccordingly. Hence, it is better to feed the reference voltage from theoutside. Further, it is preferable that the receiving circuit is an NMOStype differential receiving circuit for receiving an input signalthrough the effect of the NMOS. If this type receiving circuit is usedas the reference voltage, the voltage of the terminating power supply isused. In this case, the reference voltage is equal to half of a supplyvoltage. Hence, it is possible to receive a small amplitude waveform of1 V or less around the reference voltage.

For example, under the following condition, the amplitude at receivingcircuit is 0.68V. Specifically, if each of the resistances ofterminating resistors 50, 51 is 50 ohms, each of the resistances ofmatching resistors 80, 81, 82 and 83 is 75 ohms and the on-resistance ofdriving circuit is 10 ohms, the supply voltage for the driving circuitis 3V, and the terminating supply voltage is 1.5V, when the drivingcircuit is at a low output, the voltage at each receiving circuit is1.16V (=1.5V−(1.5V−0)×(50Ω/2)/(50Ω/2+75Ω+10)=1.5−0.34) and when thedriving circuit is at a high output, the voltage at each receivingcircuit is 1.84V (=1.5V+(3−1.5)×(50/2)/(50/2+75+10)=1.5+0.34). Thus, theamplitude at each receiving circuit is 0.68V (=1.84−1.16).

In FIG. 4, just one receiving circuit 32 to 34 of each circuit block isdescribed by way of example. However, the present invention is notlimited by the number of the receiving circuits.

In the signal transmission circuit arranged as described above, theresistance of each of the resistors 80 to 83 is made equal to a valuederived by subtracting a half of an impedance of the line 100 from animpedance of the intra-block transmission line 11. The impedance of theline 100 is required to be halved, because the signal from the drivingcircuit block is branched into two ways at a contact point B with thebus 100. That is, the following expression is established:Rm=Zs−Z0/2   (1)where Zs denotes an impedance of the transmission line 11, Z0 denotes animpedance of the line 100, and Rm denotes a resistance of the resistor80.

As is understood from this expression, the total impedance of theresistor 80 and the line 100 as viewed from the transmission line 11 ismade equal to the impedance of the transmission line 11 itself. Thismakes it possible to prevent repetitive reflections inside of a branchedline.

The resistors 81 to 83 may be defined by the similar method. As such,another block may have the same effect as the foregoing block 1.

Next, to describe the effect of the resistor derived by the expression(1), the kind of waveform which is transmitted to each point of FIG. 4when the driving circuit 21 is switched from a Low output to a Highoutput will be discussed below with reference to the circuit diagram ofFIG. 4.

First, it is necessary to derive a potential of the transmission line100 occurring when the driving circuit 21 feeds a Low output. Thevoltage of the transmission bus is made equal to the voltage derived bydividing the terminating supply voltage of 1.5 V by the terminationresistors 50 and 51, the resistor 80 and the on resistance of thedriving circuit 21. Concretely, the voltage at the point B on thetransmission line when the driving circuit 21 provides a Low output isas follows:1.5V×(75Ω+10Ω)/(10Ω+75Ω+25Ω)=1.16 (V)

In the circuit of FIG. 4, the signal driven from the driving circuit 21is not reflected at the B point. Therefore, the overall signal istransmitted to the transmission line 100. The potential of the signaltransmitted to the point B when the output of the driving circuit isswitched from Low to High is equal to the voltage given by dividing theterminating supply voltage of 1.5 V and the supply voltage of 3 V of thedriving circuit 21 by the terminating resistors 50 and 51, the resistor80, and the on resistance of the driving circuit 21. Hence, the signalpotential at the B point when the driving circuit 21 provides a Highoutput is derived as follows:1.5V+(3V−1.5V)×25Ω/(10Ω+75Ω+25Ω)=1.84 VThat is, the amplitude of the signal transmitted to the point B is;1.84V−1.16V=0.68V

When the signal of the amplitude of 0.68 V transmitted to thetransmission line 100 reaches the point C, though the transmission lineof 50Ω, the resistor of 75Ω and the transmission bus of 100Ω are viewedin the front, the mismatch of the impedance brings about reflection,because the total impedance of 38.9Ω of these two lines is differentfrom the impedance of 50Ω of the transmission line through which thesignal passes. The transmittance coefficient is: 1− the reflectioncoefficient=1−1−(50−38.9)/(50+38.9)=0.875

The potential of the signal passing through the point C is equal to thevalue derived by multiplying the signal amplitude of 0.68 V at the pointB by the transmittance coefficient of 0.875 and adding an initialpotential to the multiplied value. That is, the potential of the signalis:0.68V×0.875+1.16V=1.76 VSimilar reflections take place at the point E or the point G. Thepotential at the E or the G point are 1.68 V and 1.61 V, respectively.

These results are shown in FIGS. 7A to 7C. FIG. 7A shows signalwaveforms which come to and go out of the point C, that is, the signalwaveform at the point B which comes to the point C and the signalwaveforms at the points D and E which go out of the point C. Likewise,FIG. 7B shows signal waveforms which come to and go out of the point E.FIG. 7C shows signal waveforms which come to and go out of the point G.In FIGS. 7A-7C, a numeral 702 denotes a signal waveform at the point Bin FIG. 4. A numeral 703 denotes a signal waveform at the point C. Anumeral 704 denotes a signal waveform at the point D. A numeral 705denotes a signal waveform at the point E. A numeral 706 denotes a signalwaveform at the point F. A numeral 707 denotes a signal waveform at thepoint G. A numeral 708 denotes a signal waveform at the point H. Whenthe signal drops, the same thing occurs. The signal waveforms at thistime are shown in FIGS. 8A to 8C. In FIGS. 8A to 8C, numerals 702 to 708denote the signal waveforms from the point B to the point H as in FIG.4.

In the case of using the signal transmitting circuit clearly describedin this embodiment, it is understood that it is possible for any firstsignal indicating a High level from the driving circuit 21 at eachbranch point to exceed the reference voltage (1.5 V in the abovecondition). Therefore, each receiving circuit will be able to recognizethe High level being sent.

Such an effect of this invention is sufficiently brought about by theresistance for resistors 80 to 83 derived by the expression (1) as wellas any value close to the resistance derived by the expression (1).

This will be described with reference to FIGS. 24 to 26. FIG. 24 showsthe waveforms at the points A, C, D, G and H in FIG. 4 through therelation between a time and a voltage as the sending circuit 21continues to output a pulse waveform in the circuit arrangement shown inFIG. 4 in which the inter-block transmission line (main transmissionline) 100 has an impedance of 50Ω, each of the intra-block transmissionlines 11 to 14 has an impedance of 100Ω, each of the terminatingresistors 50 and 51 has a resistance of 50Ω, the terminating supplyvoltage is 1.65 V and each of the resistors 80 to 83 has a resistance of75Ω obtained by the expression (1).

In FIG. 24, a numeral 701 denotes a signal waveform at the point A. Anumeral 703 denotes a signal waveform at the point C. A numeral 704denotes a signal waveform at the point D. A numeral 707 denotes a signalwaveform at the point G. A numeral 708 denotes a signal waveform at thepoint H. It is difficult to visually separate the curve indicated by 707from the curve indicated by 708, because both of the curves areoverlapped with each other.

On the other hand, the other condition is illustrated in FIG. 25. FIG.25 shows a waveform when each resistance of the resistors 80 to 83 ischanged to 50Ω for obtaining a larger amplitude. As in FIG. 25, numerals701, 703, 704, 707 and 708 show the waveforms at the points A, C, D, Gand H as in FIG. 4, respectively. The resistance 50Ω used herein is only66% of the resistance of 75Ω obtained by the expression (1). As can beseen from FIG. 25, such resistance values may be used without anytrouble.

If the impedance of the intra-block line is 75Ω, each resistance of theresistors 80 to 83 may be fixed to 75Ω for keeping the signal amplitudethe same as the value of FIG. 24. The waveform for this case is shown inFIG. 26. In this case, each resistance of the resistors 80 to 83 islarger than the resistance of 50Ω obtained by the expression (1) by afactor of 50%. With regard to this, it should be noted if eachresistance of the resistors 80 to 83 is shifted to and fro by about 50%relative to the value obtained by the expression (1), the effect of thepresent application can still be achieved.

Further, to enhance the effect of the invention, it is preferable to setthe resistances of the resistors 80 to 83 to be a higher value than theimpedance of the main transmission line 100. In addition, when thetransmission line 100 has many branch lines, the signal from the drivingcircuit 21 cannot exceed the reference voltage even through the effectof the signal transmitting circuit used in this embodiment. A method forcoping with this shortcoming will be clarified in the embodiment 3.

Each signal which enters into the transmission lines 12 to 14 at thepoints C, E and G is mirror-reflected on the corresponding receivingcircuit and then returns to the branch point. Since this circuit keepsthe impedances properly matched, the overall signal is transmitted tothe transmission line 100 at one time without reflection of the signalon the branch point.

As is obvious from this figure, the resistors inserted in the presentinvention make it possible to greatly reduce the potential dropresulting from the reflection. Further, tnese resistors make the signalpotential drop in a remote receiving circuit from the driving circuitnegligible.

By inserting a resistor having a predetermined resistance around acontact between the transmission line inside of the circuit block andthe inter-block transmission line, it is possible to keep the signalamplitude on the transmission bus smaller and transmit the signal athigh speed. How much the amplitude is made smaller is allowed to befreely designed by changing the impedances of the transmission line 100and each intra-block transmission line. For example, if the sendingcircuit 21 has an on resistance of 10Ω, assuming that the intra-blocktransmission line has an impedance of 100Ω and the transmission line 100has an impedance of 25Ω, the signal amplitude of the transmission bus iscalculated as follows: 1.5V×12.5Ω/(12.5Ω+87.5Ω+10Ω)×2=0.34 (V) in whic.heach of the resistors 80 to 83 has a resistance of 87.5Ω. The waveformsat this case are shown in FIGS. 18A to 18C and 19A to 19C. In thesefigures, numerals 702 to 708 denote the signal waveforms at the B to theH points as in FIG. 4. From this figure, it is understood that awaveform with a smaller amplitude and a small drop is obtained.

Further, the resistors 80 to 83 have an effect of suppressing loweringof the impedance of the transmission line 100 resulting from the loadcapacitance in the circuit block. That is, by inserting a resistorbetween the transmission line 100 and each of the circuit blocks 1 to 5,the inter-block transmission line is not able to see the capacitance inthe circuit block directly (i.e., the total of the transmission lineload capacitance and the capacitance of the driving and receivingcircuits). Hence, it is possible to suppress the lowering of theimpedance of the transmission line.

Moreover, the signal transmitting system of the present invention offersa further advantageous effect in a situation where a new board is addedto the transmission bus in operation or a mounted broad is pulled out,that is, if a so-called live-insertion is executed. For example,consider that a board charged up to the High level is inserted to thetransmission line to which the Low signal is transmitted. In this case,since the potential of the in-board capacitance is different from thepotential of the transmission line, current flows from the board to thetransmission line. The current flow is transmitted to the transmissionline. The flown current is further transmitted as a distorted waveforminto the receiving circuit inside of the branched line. If this waveformdistortion goes up to a higher potential than the reference voltage, thereceiving circuit recognizes that the High signal is transmitted andthus malfunctions.

To describe the effect of the waveform distortion, FIG. 9 shows awaveform occurring when the live-insertion is done in the conventionaltransmission line and FIG. 10 shows a waveform occurring when thelive-insertion is done by the transmitting circuit offered by theinvention. As shown in FIGS. 9 and 10, the waveform distortion caused bythe live-insertion is reduced by the present invention.

EMBODIMENT 2

The following description will be directed to embodiment 2 in which thepresent invention is applied to a bidirectional transmission line.

FIG. 11 is a fundamental block diagram showing the second embodiment.The circuit blocks 1 to 4 provide driving circuits 21 to 24, receivingcircuits 31 to 34, resistors 80 to 83, and transmission lines 11 to 14,respectively. A transmission line 100 is connected to the circuit blocks1 to 4 and is terminated by the resistors 50 and 51, each having aresistance equal to a characteristic impedance value of the transmissionline 100.

FIG. 11 shows the transmission line terminated at both ends by theresistors. However, if desired, the transmission bus may be terminatedat one end by one resistor. Further, FIG. 11 shows four blocks. Inactuality, the present invention may apply to any transmission line ifit is connected to two or more blocks.

The arrangements of the driving circuits 21 to 24 and the receivingcircuits 31 to 34 included in the circuit blocks shown in FIG. 11 arethe same as those described with reference to FIGS. 5 and 6. The valuesof the resistors 80 to 83 are allowed to be defined by the manner of theembodiment 1 indicated in FIG. 4. Further, assuming that the circuitblock 1 operates to issue a signal, the signal waveforms at the points Ato H are the same as those of the embodiment 1.

In the arrangement having the driving circuit and the receiving circuitin one circuit block indicated in the embodiment 2, by making theresistance equal to or close to the resistance obtained by the previousexpression (1), it is possible to reduce the waiting time accompaniedwith switching of the driving circuit. Later, in the circuit arrangementshown in FIG. 11, the change of the signal waveform occurring when thedriving circuit is switched will be described below.

At first, the driving circuit is switched in accordance with thefollowing procedure.

(1) The driving circuit 21 outputs a High signal.

(2) 10 ns later than (1), the driving circuit 21 is switched to a highimpedance state. At this time, the driving circuit 24 outputs a Highsignal.

After the driving circuit 21 is switched, the terminating potentialdrops the signal potential on the transmission line located close to thedriving circuit 21 until the High signal from the driving circuit 24reaches that part of the transmission line. Hence, the dropped waveformis transmitted to each branched line through the transmission line.

The dropped waveform at each point occurring in the case of theconventional transmission line with no resistor is shown in FIGS. 12Aand 12B, while the dropped waveform at each point estimated about thetransmission line of the present invention is shown in FIGS. 13A and13B. The waveforms in these figures are those at the input circuit blockof the receiving circuit 32 included in a circuit block 2 adjacent to acircuit block 1 having the driving circuit 21.

As is obvious from FIGS. 12A and 12B, in the conventional transmissionline, the overlapped adverse effects of repetitive reflections in thebranched line and the dropped signal caused by switching the drivingcircuit result in delaying when the receiving circuit reads an inputsignal, that is, 2Td later than when the driving circuit is switched. Tdindicated a time when a signal is transmitted from one end to the otherend of the transmission line. Herein, Td is about 6 ns.

On the other hand, the transmission line according to the presentinvention needs only a delay of Td after the driving circuit is switchedbefore the receiving circuit reads the input signal. That is, thepresent invention provides a capability of reducing a waiting timerequired to read the input signal after the driving circuit is switchedfron 2 Td to Td.

The foregoing embodiment has been described for High to High switching.This operation holds true to all kinds of switchings such as Low to Low,Low to High, and High to Low. Further, this effect is active in anycombination without depending on a driving circuit to be switched.

EMBODIMENT 3

The following description will be directed to a third embodiment whichis particularly effective in the case of providing a large capacitanceat the tip of each branched line in a situation where there are manybranched lines. FIG. 14 is a fundamental block diagram for explaining aunidirectional transmission bus according to this embodiment. FIG. 15 isa fundamental block diagram for explaining a bidirectional transmissionbus according to this embodiment. In FIG. 14, a circuit block 1 includesa driving circuit 21, and circuit blocks 2 to 4 include receivingcircuits 32 to 34, respectively. Further, the blocks have resistors 80to 83 and transmission lines 11 to 14, respectively. In FIG. 15, thecircuit blocks 1 to 4 provide sending circuits 21 to 24, receivingcircuits 31 to 34, resistors 80 to 83, and transmission lines 11 to 14,respectively. In FIGS. 14 and 15, the transmission line 100 is connectedto the circuit blocks 1 to 4, and is terminated by resistors 50 and 51each having a resistance equivalent to a characteristic impedance valueof the transmission line 100.

In FIGS. 14 and 15, the transmission line is terminated at both ends bythe resistors. However, if preferred, the transmission line may beterminated at one end by one resistor. Further, in FIGS. 14 and 15, thenumber of blocks is 4. In actuality, the present invention is applicableonly if two or more blocks are provided.

Incidentally, in these figures numerals 90 to 93 denote switches.Numerals 110 to 113 denote resistors.

In this embodiment, the operation and the effect of the switches will bedescribed with reference to the fundamental block diagrams of FIGS. 14and 15. The other parts of this third embodiment are the same as thoseof the embodiments 1 and 2. Therefore, description about such otherparts is not provided here to avoid redundancy.

If the capacitance at the tip of the branched line is great or if alarge number of branched lines are provided, the drop of the signalpotential at the branch point of the transmission line is unacceptablylarge. Even the embodiments 1 and 2 are unable to suppress such a largedrop.

For example, consider the condition indicated in the embodiment 1, thatis, the circuit arranged so that in FIG. 4 the transmission line 100 hasan impedance of 50Ω, each branched line 11 to 14 has an impedance of100Ω, each of the terminating resistors 50 and 51 has a resistance of50Ω, each of the termination power supply has a voltage of 1.5 V, eachof the resistors 80 to 83 has a resistance of 75Ω, the on resistance ofthe sending circuit 21 is 10Ω, the driving circuit 21 operates toconnect the transmission bus to a 3-V power supply when the circuit 21feeds a High signal, and the driving circuit 21 operates to connect thetransmission bus to the ground or 0-V supply when the circuit feeds aLow signal. In such a time, if seven or more branched lines areprovided, the first signal from the sending circuit 21 indicating a Highlevel will not exceed the reference voltage (Vref) after the sixthbranch point.

To overcome this shortcoming, the third embodiment will be described asa method of eliminating a delaying time caused by a dropped signalpotential. This is accomplished by passing more current than an amountof current necessary for compensating the drop of the signal potentialat the branch point.

At first referring to FIG. 14, when the driving circuit 21 is operated,the switch 90 in the circuit 1 closes to lower the resistance betweenthe transmission line 100 and the intra-block signal transmission line11. This makes it possible to increase a signal amplitude on the bus100. The same holds true for the operation of the driving circuits 21 to24 and their corresponding switches 90 to 93 in FIG. 15.

For example, on the condition that each of the terminating resistors 50and 51 has a value of 50Ω, each of matching resistors 80 to 83 has avalue of 75Ω, each of the sending circuits 21 to 25 has an on resistanceof 10Ω, and each of the switch resistors 80 to 83 has a value of 10Ω, byclosing the switch 90, the resistance between the transmission line 100and the branched line 11 is decreased from 75Ω to 8.8Ω and the amplitudeon the transmission bus 100 is increased from 0.68 V to 1.3 V. Thisresults in eliminating the delay time caused by the dropped signalpotential at the branch point.

To transfer the signal at high speed if the signal is reversed at thenext cycle, the switch is enabled to open 0.3 cycle later than thestarting time for outputting a signal from the driving circuit. By this,the signal amplitude is allowed to be returned to the predeterminedvalue, that is, a suitably small amplitude for enabling the fasttransfer. Of course, the delay could be set to be different than 0.3cycle, where appropriate.

FIGS. 16A to 16C and 17A to 17C are the drawings for explaining theeffect of this invention. The waveforms shown in these figures are thoseoccurring when the driving circuit 21 is enabled by the circuits shownin FIGS. 14 and 15. FIGS. 16A to 16C show the waveforms on the rise.FIGS. 17A to 17C show the waveforms on the drop. For purposes ofexample, the resistance of resistors 110 through 113 was set at 20Ω eachfor arriving at these waveforms.

FIGS. 16A and 17A show the signal waveforms which come to and go out ofthe point C shown in FIG. 14, that is, the waveform at the point B whichcomes to the point C and the waveforms at the points B and E which goout of the point C. Likewise, FIGS. 16B and 17B show the signalwaveforms which come to and go out of the point E. FIGS. 16C and 17Cshow the signal waveforms which come to and go out of the point G. Anumeral 1402 denotes the signal waveform at the point B shown in FIG.14. A numeral 1403 denotes the signal waveform at the point C. A numeral1404 denotes the signal waveform at the point D. A numeral 1405 denotesthe signal waveform at the point E. A numeral 1406 denotes the signalwaveform at the point G. A numeral 1408 denotes the signal waveform atthe point H.

The use of the switch makes it possible to increase the signal amplitudeon the transmission line 100 and to eliminate the delay time caused bythe dropped signal potential at the branch point. As described above,the switch control makes it possible to transfer a signal of a smallamplitude at fast speed even in a transmission line having large loadcapacitance or a large number of branched lines. Though the switchcontrol is not shown, the switch is controlled by a control unitincluded in the circuit block having the driving circuit in accordancewith conventional switching techniques.

In place of the resistors 110 to 113, similar effects can be offered byusing capacitors. Embodiments arranged to use such capacitors are shownin FIGS. 20 and 21. FIG. 20 shows the same arrangement as that shown inFIG. 14 in which a capacitor 120 is used in place of the resistor 110.FIG. 21 shows the same arrangement as that shown in FIG. 15 in whichcapacitors 120 to 123 are used in place of resistors 110 to 113. It ispreferable that the capacitance, in general, is about several tens ofpico-farads.

If the potential on the capacitor driving side is changed on the signalfrom the sending circuit, the potential of the capacitor on thetransmission line 100 will also rise according to the chargeconservation law. Hence, a larger amplitude can be obtained relative tothe amplitude changed only through the resistors 80 to 83.

With regard to the switches, it is preferable to close the switchcontained in the unit for operating the driving circuit and open theother switches. Further, the signal amplitude on the transmission bus100 is increased through the effect of the capacitor line and isreturned to the initial amplitude through the effect of the terminals 50and 51 in about several nano seconds. Hence, while the driving circuitis in operation, the switches may be kept closed.

FIGS. 22A to 22C and 23A to 23C show the rising waveform and thedropping waveform at each point when the driving circuit 21 is operatedin the circuit diagram of FIG. 20. In FIGS. 22A to 22C and 23A to 23C,FIGS. 22A and 23A show the signal waveforms which come to and go out ofthe point C of FIG. 20, that is, the signal waveform on the point Bwhich comes to the point C and the signal waveforms on the points D andE which go out of the point C. Likewise, FIGS. 22B and 23B show thesignal waveforms which come to and go out of the point E. FIGS. 22C and23C show the signal waveforms which come to and go out of the point G.In these figures, a numeral 2002 denotes the signal waveform at thepoint B of FIG. 20. A numeral 2003 denotes the signal waveform at thepoint C. A numeral 2004 denotes the signal waveform at the point D. Anumeral 2005 denotes the signal waveform at the point E. A numeral 2006denotes the signal waveform at the point F. A numeral 2007 denotes thesignal waveform at the point G. A numeral 2008 denotes the signalwaveform at the point H.

As described above, the signal amplitude on the transmission line 100 isallowed to be increased through the effect of the capacitors, therebyeliminating the delay time caused by the dropped signal potential at abranch point.

EMBODIMENT 4

FIG. 27 shows an embodiment in which the driving circuit and thereceiving circuit are integrated so that an inter-circuit blocktransmission line is connected to an intra-circuit block transmissionline through an transmission bus like a lead of an integrated circuit.

In FIG. 27, a numeral 5 denotes an inner circuit block (an inner unit,for example, an integrated circuit) which is mounted on a circuit block1 (for example, a board having an integrated circuit mounted thereon).Numerals 6 to 8 denote inner circuit blocks having receiving circuits 32to 34, respectively, which inner circuit blocks are mounted inside ofthe circuit blocks 2 to 4, respectively. The circuit blocks 1 to 4 haveresistors 80 to 83 and transmission lines 11 to 14 and 41 to 44,respectively. The transmission lines 11 to 14 are designed to have thesame or almost the same characteristic impedance as that of thetransmission lines 41 to 44. Further, the transmission line 100 has thecircuit blocks 1 to 4 connected thereto and is terminated at both endsby the resistors 50 and 51 having a resistance equal to or close to thesame characteristic impedance as that of the transmission line 100.

Also in this embodiment, the transmission line may be terminated at oneend by one resistor. The necessary number of the receiving circuitblocks is one or more.

FIG. 28 shows a section of a QFP (Quad Flat Package) package. FIG. 29shows a section of a PGA (Pin Grid Array) package. In FIG. 28, when adriving signal is to be provided, a chip 130 serving as a drivingcircuit operates to output a signal by way of bonding wires 140, 141 andlead frames 120, 121, in sequence. When receiving the signal, the chip130 receives the signal by way of the lead frames 120, 121 and thebonding wires 140, 141, in sequence. In FIG. 29, when a driving signalis provided, the chip 131 operates to output a signal by way of bondingwires 142, 143, in-package wire patterns 170, 171, and I/O pins 160, 161in sequence. When receiving a signal, the chip 131 receives a signal ina way of the I/O pins 160, 161, the in-package wire patterns 170, 171,and the bonding wires 142, 143 in sequence. In FIGS. 28 and 29, the leadframes 120, 121, the in-package wire patterns 170, 171 and the I/O pins160, 161 need to have the characteristic impedance matching described inthe present invention.

In general, the characteristic impedance of the board often takes avalue of 60 to 100Ω. Hence, the most preferable method is that the leadframes 120, 121 and the in-package wire patterns 170, 171 are designedto each have a characteristic impedance value in the range of 60 to100Ω.

To describe how the above components correspond to the portions shown inFIG. 27, the sending circuit 21 and the receiving circuits 32 to 34correspond to the chips 130 and 131. The transmission lines 41 to 44correspond to the lead frames 120, 121, the in-package wire patterns170, 171 and the I/O pins 160, 161. The inner circuit blocks 5 to 8correspond to the QFP package and the PGA package itself. In addition tothe package form shown in FIGS. 28 and 29, any package form may be takenonly if the substantially similar components are integrated.

FIG. 30 shows a model on which the QFP package of FIG. 28 is mounted.The model of FIG. 30 is arranged so that four boards 190 to 193 aremounted on a mother board 180 through connectors 200 to 203. As thecorresponding portions to those shown in FIG. 27, the transmission lines11 to 14 correspond to transmission lines 230 to 233, the matchingresistors 80 to 83 correspond to matching resistors 210 to 213. Theinter-circuit block transmission line 100 corresponds to a data bus 240.The terminating resistors 50, 51 correspond to terminating resistors220, 221. In addition, in FIG. 30, the transmission lines 230 to 233 runon the outer layer of the board. On the other hand, those lines may beformed on the inner layer. In the arrangement shown in FIG. 30, thenumber of boards to be mounted is not limited. Further, a similarcircuit may be composed on just one board without the mother board.

According to the present embodiment, for matching the impedances witheach other, the components having larger packaging capacitance andinductance such as a logic LSI are more effective.

In this embodiment, each inner circuit block has just one drivingcircuit or receiving circuit. Like the embodiment 2, on the other hand,one inner circuit block may have both of the driving circuit and thereceiving circuit.

The present invention offers new ideas in light of the method ofdesigning or manufacturing an integrated circuit such as an IC or an LSIor a module such as a memory. Previously, the process of designing ormanufacturing such devices, the impedance of a transmission line on theboard to be mounted has not been considered at all. According to thepresent invention, in the process of designing or manufacturing suchdevices, the following new designing and manufacturing process is taken:

-   -   (1) Define an impedance of a transmission line of a board to be        mounted.    -   (2) Define an impedance of a transmission line on a board on        which a transmission line such as a lead frame for an integrated        circuit to be designed is to be connected. (Define an impedance        on each lead frame. If the transmission line on the board is        constant, follow it.)    -   (3) The transmission bus is manufactured according to the        impedance of the designed transmission and then is connected to        an integrated circuit chip by using a wire-bonding technique,        for example.    -   (4) Mount the transmission line on the right place of the board.

Based on this manufacturing method, it is possible to manufacture anintegrated circuit or a signal transmitting circuit-which is suitable tofast transmission.

It is to be understood that the above-described arrangements are simplyillustrative of the application of the principles of the presentinvention. Numerous other arrangements may be readily devised by thoseskilled in the art which will embody the principles of the invention andfall within its spirit and scope.

1. A signal transmitting device comprising: a main transmission lineterminated at only one end thereof; a mother board on which the maintransmission line is formed; a first integrated circuit to receive asignal; and a first connector adapted to connect the mother board to afirst daughter board which comprises: a second integrated circuit todrive the signal, and a first intra-board line to transmit the signaloutput from the second integrated circuit to the main transmission line,and a first resistor coupled with the main transmission line and withthe first intra-board line, the first resistor having a resistance valueto reduce signal reflection between the main transmission line and thefirst intra-board line.
 2. A signal transmitting device according toclaim 1, wherein the first resistor has a resistance value to provideimpedance matching between the main transmission line and the firstintra-board line.
 3. A signal transmitting device according to claim 1,wherein the first resistor suppresses signal reflection between the maintransmission line and the first intra-board line.
 4. A signaltransmitting device according to claim 1, wherein the first resistor hasa resistance value substantially equal to a value derived by subtractinga half of an impedance of the main transmission line from apredetermined impedance of the first intra-board line.
 5. A signaltransmitting device according to claim 4, wherein the resistance valueis 0.5 times to 1.5 times of the derived value.
 6. A signal transmittingdevice according to claim 1, wherein the impedance of the firstintra-board line is higher than the impedance of the main transmissionline.
 7. A signal transmitting device according to claim 1, wherein thesecond integrated circuit includes an output circuit of a push-pull typeto drive the signal.
 8. A signal transmitting device according to claim1, wherein the second integrated circuit is comprised of an elementhaving a switching function, the element being connected to a powersupply and a ground, and wherein the minimum resistance of the elementis 50 ohms or less.
 9. A signal transmitting device according to claim1, wherein the second integrated circuit is a memory.
 10. A signaltransmitting device according to claim 1, wherein the main transmissionline is terminated with an element having a resistance substantiallyequal to an impedance value of the main transmission line itself.
 11. Asignal transmitting device according to claim 1, further comprising: asecond intra-board line to transmit the signal from the maintransmission line to the first integrated circuit, a second resistorcoupled with the main transmission line and with the second intra-boardline.
 12. A signal transmitting device according to claim 11, whereinthe second resistor has a resistance value to provide impedance matchingbetween the main transmission line and the second intra-board line. 13.A signal transmitting device according to claim 11, wherein the secondresistor suppresses signal reflection between the main transmission lineand the second intra-board line.
 14. A signal transmitting deviceaccording to claim 11, wherein the second resistor has a resistancevalue substantially equal to a value derived by subtracting a half of animpedance of the main transmission line from a predetermined impedanceof the intra-board line.
 15. A signal transmitting device according toclaim 14, wherein the resistance value is 0.5 times to 1.5 times of thederived value.
 16. A signal transmitting device according to claim 11,wherein the impedance of the second intra-board line is higher than theimpedance of the main transmission line.
 17. A signal transmittingdevice according to claim 11, wherein the first integrated circuit is amemory.
 18. A signal transmitting device according to claim 11, furthercomprising a second daughter board, the second daughter board mountingthe first integrated circuit, the second intra-board line and the secondresistor, and a second connector which connects the mother board and thesecond daughter board.
 19. A signal transmitting device comprising: afirst transmission line, terminated at only one end thereof; a motherboard on which the first transmission line formed; a first integratedcircuit to receive a first signal and to drive a second signal; and afirst connector through which a first daughter board is capable of beingmounted on the mother board, wherein the first daughter board comprises:a second integrated circuit to drive the first signal and to receive thesecond signal, a second transmission line to transmit the first andsecond signals between the second integrated circuit and the firsttransmission line, and a first resistor coupled with the firsttransmission line and with the second transmission line, the firstresistor having a resistance value to reduce signal reflection betweenthe first transmission line and the second transmission line.
 20. Asignal transmitting device according to claim 19, wherein the firstresistor has a resistance value to provide impedance matching betweenthe first transmission line and the second transmission line.
 21. Asignal transmitting device according to claim 19, wherein the firstresistor suppresses signal reflection between the first transmissionline and the second transmission line.
 22. A signal transmitting deviceaccording to claim 19, wherein the first resistor has a resistance valuesubstantially equal to a value derived by subtracting a half of animpedance of the first transmission line from a predetermined impedanceof the second transmission line.
 23. A signal transmitting deviceaccording to claim 22, wherein the resistance value is 0.5 times to 1.5times of the derived value.
 24. A signal transmitting device accordingto claim 19, wherein the impedance of the second transmission line ishigher than the impedance of the first transmission line.
 25. A signaltransmitting device according to claim 19, wherein the second integratedcircuit includes an output circuit of push-pull type for driving asignal.
 26. A signal transmitting device according to claim 19, whereinthe integrated circuit is comprised of an element having a switchingfunction, the element being connected to a power supply and a ground,and wherein the minimum resistance of the element is 50 ohms or less.27. A signal transmitting device according to claim 19, wherein thesecond integrated circuit includes a differential input circuit.
 28. Asignal transmitting device according to claim 27, wherein a referencevoltage used in the differential input circuit is supplied from theoutside of the second integrated circuit.
 29. A signal transmittingdevice according to claim 19, wherein the second integrated circuit is amemory.
 30. A signal transmitting device according to claim 19, whereinthe first transmission line is terminated with an element having aresistance substantially equal to an impedance value of the firsttransmission line itself.
 31. A signal transmitting device according toclaim 19, further comprising: a third transmission line to transmit thefirst and second signals between the first transmission line and thefirst integrated circuit, and a second resistor coupled with the firsttransmission line and with the third transmission line.
 32. A signaltransmitting device according to claim 31, wherein the second resistorhas a resistance value to provide impedance matching between the firsttransmission line and the third transmission line.
 33. A signaltransmitting device according to claim 31, wherein the second resistorsuppresses signal reflection between the first transmission line and thethird transmission line.
 34. A signal transmitting device according toclaim 31, wherein the second resistor has a resistance valuesubstantially equal to a value derived by subtracting a half of animpedance of the first transmission line from a predetermined impedanceof the third transmission line.
 35. A signal transmitting deviceaccording to claim 34, wherein the resistance value is 0.5 times to 1.5times of the derived value.
 36. A signal transmitting device accordingto claim 31, wherein the impedance of the third transmission line ishigher than the impedance of the first transmission line.
 37. A signaltransmitting device according to claim 31, wherein the first integratedcircuit is a memory.
 38. A signal transmitting device according to claim31, further comprising a second daughter board, the second daughterboard mounting the first integrated circuit, the second transmissionline, and the first resistor, and a second connector through which thesecond daughter board is mounted on the mother board.
 39. A signaltransmitting device comprising: a first transmission line terminated atonly one end thereof; a mother board on which the first transmissionline is formed; a first integrated circuit to receive a signal; and afirst connector being capable of connecting a first daughter board tothe mother board, wherein the first daughter board comprises: a secondintegrated circuit to drive the signal, a second transmission line totransmit the signal output from the second integrated circuit to thefirst transmission line, and a first resistor coupled with the firsttransmission line and with the second transmission line, the firstresistor having a resistance value to reduce signal reflection betweenthe first transmission line and the second transmission line.
 40. Asignal transmitting device according to claim 39, wherein the firstresistor has a resistance value to provide impedance matching betweenthe first transmission line and the second transmission line.
 41. Asignal transmitting device according to claim 39, wherein the firstresistor suppresses signal reflection between the first transmissionline and the second transmission line.
 42. A signal transmitting deviceaccording to claim 39 wherein the first resistor has a resistance valuesubstantially equal to a value derived by subtracting a half of animpedance of the first transmission line from a predetermined impedanceof the second transmission line.
 43. A signal transmitting deviceaccording to claim 42, wherein the resistance value is 0.5 times to 1.5times of the derived value.
 44. A signal transmitting device accordingto claim 39, wherein the impedance of the second transmission line ishigher than the impedance of the first transmission line.
 45. A signaltransmitting device according to claim 39, wherein the second integratedcircuit includes an output circuit of push-pull type to drive a signal.46. A signal transmitting device according to claim 39, wherein thesecond integrated circuit is comprised of an element having a switchingfunction, the element being connected to a power supply and a ground,and wherein the minimum resistance of the element is 50 ohms or less.47. A signal transmitting device according to claim 39, wherein thesecond integrated circuit is a memory.
 48. A signal transmitting deviceaccording to claim 39, wherein the first transmission line is terminatedwith an element having a resistance substantially equal to an impedancevalue of the first transmission line itself.
 49. A signal transmittingdevice according to claim 39, further comprising: a third transmissionline to transmit the signal from the first transmission line to thefirst integrated circuit, and a second resistor coupled with the firsttransmission line and with the third transmission line.
 50. A signaltransmitting device according to claim 49, wherein the second resistorhas a resistance value to provide impedance matching between the firsttransmission line and the third transmission line.
 51. A signaltransmitting device according to claim 49, wherein the second resistorsuppresses signal reflection between the first transmission line and thethird transmission line.
 52. A signal transmitting device according toclaim 49, wherein the second resistor has a resistance valuesubstantially equal to a value derived by subtracting a half of animpedance of the first transmission line from a predetermined impedanceof the third transmission line.
 53. A signal transmitting deviceaccording to claim 52, wherein the resistance value is 0.5 times to 1.5times of the derived value.
 54. A signal transmitting device accordingto claim 49, wherein the impedance of the third transmission line ishigher than the impedance of the first transmission line.
 55. A signaltransmitting device according to claim 49, wherein the first integratedcircuit is a memory.
 56. A signal transmitting device according to claim49, further comprising a second daughter board, the second daughterboard mounting the first integrated circuit, the third transmission lineand the second resistor, and a second connector to connect the seconddaughter board and the mother board.
 57. A signal transmission deviceaccording to claim 11, wherein the second resistor has a resistancevalue to reduce signal reflection between the main transmission line andthe second intra-board line.
 58. A signal transmitting device accordingto claim 31, wherein the second resistor has a resistance value toreduce signal reflection between the first transmission line and thethird transmission line.
 59. A signal transmitting device according toclaim 49, wherein the second resistor has a resistance value to reducesignal reflection between the first transmission line and the thirdtransmission line.
 60. A signal transmitting device according to claim1, wherein the first resistor is disposed nearer to the first connectorthan it is to the second integrated circuit.
 61. A signal transmittingdevice according to claim 19, wherein the first resistor is disposednearer to the first connector than it is to the second integratedcircuit.
 62. A signal transmitting device according to claim 39, whereinthe first resistor is disposed nearer to the first connector than it isto the second integrated circuit.
 63. A signal transmitting deviceaccording to claim 18, wherein the second resistor is disposed nearer tothe second connector than it is to the first integrated circuit.
 64. Asignal transmitting device according to claim 38, wherein the secondresistor is disposed nearer to the second connector than it is to thefirst integrated circuit.
 65. A signal transmitting device according toclan 56, wherein the second resistor is disposed nearer to the secondconnector than it is to the integrated circuit.
 66. A signaltransmitting device comprising: a main transmission line terminated atonly one end thereof; a mother board on which the main transmission lineis formed; a first integrated circuit to receive a signal; and a firstconnector adapted to connect the mother board to a first daughter boardwhich comprises: a second integrated circuit to drive the signal, afirst stub-line to transmit the signal output from the second integratedcircuit to the main transmission line, and a first resistor coupled withthe main transmission line and with the first stub-line.
 67. A signaltransmitting device according to claim 66, wherein the first resistorhas a resistance value to provide impedance matching between the maintransmission line and the first stub-line.
 68. A signal transmittingdevice according to claim 66, wherein the first resistor suppressessignal reflection between the main transmission line and the firststub-line.
 69. A signal transmitting device according to claim 66,wherein the first resistor has a resistance value substantially equal toa value derived by subtracting a half of an impedance of the maintransmission line from a predetermined impedance of the first stub-line.70. A signal transmitting device according to claim 69, wherein theresistance value is 0.5 times to 1.5 times of the derived value.
 71. Asignal transmitting device according to claim 66, wherein the impedanceof the first stub-line is higher than the impedance of the maintransmission line.
 72. A signal transmitting device according to claim66, wherein the second integrated circuit includes an output circuit ofa push-pull type to drive the signal.
 73. A signal transmitting deviceaccording to claim 66, wherein the second integrated circuit iscomprised of an element having a switching function, the element beingconnected to a power supply and a ground, and wherein a minimumresistance of the element is 50 ohms or less.
 74. A signal transmittingdevice according to claim 66, wherein the second integrated circuit is amemory.
 75. A signal transmitting device according to claim 66, whereinthe main transmission line is terminated with an element having aresistance substantially equal to an impedance value of the maintransmission line itself.
 76. A signal transmitting device according toclaim 66, further comprising: a second stub-line to transmit the signalfrom the main transmission line to the first integrated circuit, and asecond resistor coupled with the main transmission line and with thesecond stub-line.
 77. A signal transmitting device according to claim76, wherein the second resistor has a resistance value to provideimpedance matching between the main transmission line and the secondstub-line.
 78. A signal transmitting device according to claim 76,wherein the second resistor suppresses signal reflection between themain transmission line and the second stub-line.
 79. A signaltransmitting device according to claim 76, wherein the second resistorhas a resistance value substantially equal to a value derived bysubtracting a half of an impedance of the main transmission line from apredetermined impedance of the stub-line.
 80. A signal transmittingdevice according to claim 79, wherein the resistance value is 0.5 timesto 1.5 times of the derived value.
 81. A signal transmitting deviceaccording to claim 76, wherein the impedance of the second stub-line ishigher than the impedance of the main transmission line.
 82. A signaltransmitting device according to claim 76, wherein the first integratedcircuit is a memory.
 83. A signal transmitting device according to claim76, further comprising a second daughter board, the second daughterboard mounting the first integrated circuit, the second stub-line andthe second resistor, and a second connector which connects the motherboard to the second daughter board.
 84. A signal transmitting devicecomprising: a main transmission line terminated at only one end thereof;a mother board on which the main transmission line is formed; a firstintegrated circuit to receive a first signal and to drive a secondsignal: and a first connector through which a first daughter board iscapable of being mounted on the mother board, wherein the first daughterboard comprises: a second integrated circuit to drive the first signaland to receive the second signal, a first stub-line to transmit thefirst and second signals between the second integrated circuit and themain transmission line, and a first resistor coupled with the maintransmission line and with the first stub-line.
 85. A signaltransmitting device according to claim 84, wherein the first resistorhas a resistance value to provide impedance matching between the maintransmission line and the first stub-line.
 86. A signal transmittingdevice according to claim 84, wherein the first resistor suppressessignal reflection between the main transmission line and the firststub-line.
 87. A signal transmitting device according to claim 84,wherein the first resistor has a resistance value substantially equal toa value derived by subtracting a half of an impedance of the maintransmission line from a predetermined impedance of the first stub-line.88. A signal transmitting device according to claim 84, wherein theresistance value is 0.5 times to 1.5 times of the derived value.
 89. Asignal transmitting device according to claim 84, wherein the secondintegrated circuit includes a push-pull type output circuit to drive asignal.
 90. A signal transmitting device according to claim 84, whereinthe second integrated circuit is comprised of an element having aswitching function, the element being connected to a power supply and aground, and wherein a minimum resistance of the element is 50 ohms orless.
 91. A signal transmitting device according to claim 84, whereinthe second integrated circuit includes a differential input circuit. 92.A signal transmitting device according to claim 91, wherein a referencevoltage used in the differential input circuit is supplied from theoutside of the second integrated circuit.
 93. A signal transmittingdevice according to claim 84, wherein the second integrated circuit is amemory.
 94. A signal transmitting device according to claim 84, whereinthe main transmission line is terminated with an element having aresistance substantially equal to an impedance value of the maintransmission line itself.
 95. A signal transmitting device according toclaim 84, further comprising: a second stub-line to transmit the firstand second signals between the main transmission line and the firstintegrated circuit, and a second resistor coupled with the maintransmission line and with the second stub-line.
 96. A signaltransmitting device according to claim 95, wherein the second resistorhas a resistance value to provide impedance matching between the maintransmission line and the second stub-line.
 97. A signal transmittingdevice according to claim 95, wherein the second resistor suppressessignal reflection between the main transmission line and the secondstub-line.
 98. A signal transmitting device according to claim 95,wherein the second resistor has a resistance value substantially equalto a value derived by subtracting a half of an impedance of the maintransmission line from a predetermined impedance of the secondstub-line.
 99. A signal transmitting device according to claim 98,wherein the resistance value is 0.5 times to 1.5 times of the derivedvalue.
 100. A signal transmitting device according to claim 95, whereinthe impedance of the second stub-line is higher than the impedance ofthe main transmission line.
 101. A signal transmitting device accordingto claim 95, wherein the first integrated circuit is a memory.
 102. Asignal transmitting device according to claim 95, further comprising asecond daughter board, the second daughter board mounting the firstintegrated circuit, the first stub-line, and the first resistor, and asecond connector through which the second daughter board is mounted onthe mother board.
 103. A signal transmitting device comprising: a maintransmission line terminated at only one end thereof; a mother board onwhich the main transmission line is formed; a first integrated circuitto receive a signal; and a first connector being capable of connecting afirst daughter board to the mother board which comprises: a secondintegrated circuit to drive the signal, a first stub-line to transmitthe signal output from the second integrated circuit to the maintransmission line, and a first resistor coupled with the maintransmission line and with the first stub-line.
 104. A signaltransmitting device according to claim 103, wherein the first resistorhas a resistance value to provide impedance matching between the maintransmission line and the second transmission line.
 105. A signaltransmitting device according to claim 103, wherein the first resistorsuppresses signal reflection between the main transmission line and thefirst stub-line.
 106. A signal transmitting device according to claim103, wherein the first resistor has a resistance value substantiallyequal to a value derived by subtracting a half of an impedance of themain transmission line from a predetermined impedance of the firststub-line.
 107. A signal transmitting device according to claim 106,wherein the resistance value is 0.5 times to 1.5 times of the derivedvalue.
 108. A signal transmitting device according to claim 103, whereinthe impedance of the first stub-line is higher than the impedance of themain transmission line.
 109. A signal transmitting device according toclaim 103, wherein the second integrated circuit includes a push-pulltype output circuit to drive a signal.
 110. A signal transmitting deviceaccording to claim 103, wherein the second integrated circuit iscomprised of an element having a switching function, the element beingconnected to a power supply and a ground, and wherein a minimumresistance of the element is 50 ohms or less.
 111. A signal transmittingdevice according to claim 103, wherein the second integrated circuit isa memory.
 112. A signal transmitting device according to claim 103,wherein the main transmission line is terminated with an element havinga resistance substantially equal to an impedance value of the maintransmission line itself.
 113. A signal transmitting device according toclaim 103, further comprising: a second stub-line to transmit the signalfrom the main transmission line to the first integrated circuit, and asecond resistor coupled with the main transmission line and with thesecond stub-line.
 114. A signal transmitting device according to claim113, wherein the second resistor has a resistance value to provideimpedance matching between the main transmission line and the secondstub-line.
 115. A signal transmitting device according to claim 113,wherein the second resistor suppresses signal reflection between themain transmission line and the second stub-line.
 116. A signaltransmitting device according to claim 113, wherein the second resistorhas a resistance value substantially equal to a value derived bysubtracting a half of an impedance of the main transmission line from apredetermined impedance of the second stub-line.
 117. A signaltransmitting device according to claim 116, wherein the resistance valueis 0.5 times to 1.5 times of the derived value.
 118. A signaltransmitting device according to claim 113, wherein the impedance of thesecond stub-line is higher than the impedance of the main transmissionline.
 119. A signal transmitting device according to claim 113, whereinthe first integrated circuit is a memory.
 120. A signal transmittingdevice according to claim 113, further comprising a second daughterboard, the second daughter board mounting the first integrated circuit,the second stub-line and the second resistor, and a second connector toconnect the second daughter board to the mother board.
 121. A signaltransmitting device according to claim 66, wherein the first resistorhas a resistance value to reduce signal reflection between the maintransmission line and the first stub-line.
 122. A signal transmittingdevice according to claim 76, wherein the second resistor has aresistance value to reduce signal reflection between the maintransmission line and the second stub-line.
 123. A signal transmittingdevice according to claim 84, wherein the first resistor has aresistance value to reduce signal reflection between the maintransmission line and the first stub-line.
 124. A signal transmittingdevice according to claim 95, wherein the second resistor has aresistance value to reduce signal reflection between the maintransmission line and the second stub-line.
 125. A signal transmittingdevice according to claim 103, wherein the first resistor has aresistance value to reduce signal reflection between the maintransmission line and the first stub-line.
 126. A signal transmittingdevice according to claim 113, wherein the second resistor has aresistance value to reduce signal reflection between the maintransmission line and the second stub-line.
 127. A signal transmittingdevice according to claim 66, wherein the first resistor is disposednearer to the first connector than it is to the second integratedcircuit.
 128. A signal transmitting device according to claim 84,wherein the first resistor is disposed nearer to the second connectorthan it is to the second integrated circuit.
 129. A signal transmittingdevice according to claim 103, wherein the first resistor is disposednearer to the first connector than it is to the second integratedcircuit.
 130. A signal transmitting device according to claim 83,wherein the second resistor is disposed nearer to the second connectorthan it is to the first integrated circuit.
 131. A signal transmittingdevice according to claim 102, wherein the second resistor is disposednearer to the first connector than it is to the first integratedcircuit.
 132. A signal transmitting device according to claim 120,wherein the second resistor is disposed nearer to the second connectorthan it is to the first integrated circuit.
 133. A signal transmittingdevice according to claim 84, wherein the impedance of the firststub-line is higher than the impedance of the main transmission line.